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NS ESI G W D CT NE FO R ODU DED UTE PR X9520 EN TI T MM 29, UBS E CO L223 Data Sheet OT R SIBLE S 2326, IS N POS 0, ISL2 2 X958
(R)
X9521
Dual DCP, EEPROM Memory January 3, 2006 FN8207.1
Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
FEATURES * Two Digitally Controlled Potentiometers (DCP's) --100 Tap - 10k --256 Tap - 100k --Non-Volatile --Write Protect Function * 2kbit EEPROM Memory with Write Protect & Block LockTM * 2-Wire industry standard Serial Interface --Complies to the Gigabit Interface Converter (GBIC) specification * Single Supply Operation --2.7V to 5.5V * Hot Pluggable * 20 Ld TSSOP BLOCK DIAGRAM
DESCRIPTION The X9521 combines two Digitally Controlled Potentiometers (DCP's), and integrated EEPROM with Block LockTM protection. All functions of the X9521 are accessed by an industry standard 2-Wire serial interface. The DCP's of the X9521 may be utilized to control the bias and modulation currents of the laser diode in a Fiber Optic module. The 2kbit integrated EEPROM may be used to store module definition data. The features of the X9521 are ideally suited to simplifying the design of fiber optic modules which comply to the Gigabit Interface Converter (GBIC) specification. The integration of these functions into one package significantly reduces board area, cost and increases reliability of laser diode modules.
RH1
WIPER COUNTER REGISTER
RW1 RL1
8
WP
PROTECT LOGIC
7 - BIT NONVOLATILE MEMORY
CONSTAT
RH2
WIPER COUNTER REGISTER
SDA SCL
DATA REGISTER
COMMAND DECODE & CONTROL LOGIC
4
REGISTER
RW2 RL2
2kbit
8 - BIT NONVOLATILE MEMORY
EEPROM ARRAY
THRESHOLD RESET LOGIC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. (c)2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9521 Ordering Information
PART NUMBER X9521V20I-A X9521V20I-B X9521V20IZ-A (Note) X9521V20IZ-B (Note) PART MARKING X9521VIA X9521VIB X9521VZIA X9521VZIB PRESET (FACTORY SHIPPED) VTRIPx THRESHOLD LEVELS (x = 2, 3) Optimized for 3.3V system monitoring Optimized for 5V system monitoring Optimized for 3.3V system monitoring Optimized for 5V system monitoring TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 20 Ld TSSOP 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld TSSOP (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN CONFIGURATION
20 Pin TSSOP
RH2 RW2 RL2 NC NC NC WP SCL SDA VSS
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Vcc NC NC NC NC NC NC RH1 RW1 RL1
PIN ASSIGNMENT
Pin 1 2 3 Name RH2 Rw2 RL2 Function Connection to end of resistor array for (the 256 Tap) DCP 2. Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP 2. Connection to other end of resistor array for (the 256 Tap) DCP2. Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile "write" operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no "write" (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal "pulldown" resistor, thus if left floating the write protection feature is disabled. Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. Ground. Connection to other end of resistor for (the 100 Tap) DCP 1. Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP 1 Connection to end of resistor array for (the 100 Tap) DCP 1. Supply Voltage. No connect.
7
WP
8 9 10 11 12 13 20 4, 5, 6, 14, 15, 16, 17, 18, 19
SCL SDA Vss RL1 Rw1 RH1 Vcc NC
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SCL SDA Start Figure 2. Stop
Valid Start and Stop Conditions
SCL SDA Data Stable Figure 1. PRINCIPLES OF OPERATION SERIAL INTERFACE Data Change Data Stable
Valid Data Changes on the SDA Bus
Serial Stop Condition
All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus. See Figure 2.
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the X9521 operates as a slave in all applications.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKNOWLEDGE that it received the eight bits of data. Refer to Figure 3. The device will respond with an ACKNOWLEDGE after recognition of a START condition if the correct Device Identifier bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an ACKNOWLEDGE after the receipt of each subsequent eight bit word. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an ACKNOWLEDGE. If an ACKNOWLEDGE is detected and no STOP condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an ACKNOWLEDGE is not detected. The master must then issue a STOP condition to place the device into a known state.
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Serial Clock and Data
Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 1. On power-up of the X9521, the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met. See Figure 2.
3
X9521
SCL from Master Data Output from Transmitter Data Output from Receiver
1
8
9
Start Figure 3.
Acknowledge Acknowledge Response From Receiver --The next three bits (SA3 - SA1) are the Internal Device Address bits. Setting these bits to 000 internally selects the EEPROM array, while setting these bits to 111 selects the DCP structures in the X9521. The CONSTAT Register may be selected using the Internal Device Address 010. --The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed on the device being addressed (as defined in the bits SA3 - SA1). When the R/W bit is "1", then a READ operation is selected. A "0" selects a WRITE operation (Refer to Figure 4.)
DEVICE INTERNAL ADDRESSING Addressing Protocol Overview The user addressable internal components of the X9521 can be split up into three main parts: --Two Digitally Controlled Potentiometers (DCPs) --EEPROM array --Control and Status (CONSTAT) Register Depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with the Slave Address Byte being issued on the SDA pin. The Slave address selects the part of the X9521 to be addressed, and specifies if a Read or Write operation is to be performed. It should be noted that in order to perform a write operation to either a DCP or the EEPROM array, the Write Enable Latch (WEL) bit must first be set (See "BL1, BL0: Block Lock protection bits - (Nonvolatile)" on page 12.) Slave Address Byte Following a START condition, the master must output a Slave Address Byte (Refer to Figure 4.). This byte consists of three parts: --The Device Type Identifier which consists of the most significant four bits of the Slave Address (SA7 - SA4). The Device Type Identifier must always be set to 1010 in order to select the X9521.
SA7
SA6 SA5
SA4
SA3
SA2
SA1
SA0
101
DEVICE TYPE IDENTIFIER
0
INTERNAL DEVICE ADDRESS
R/W
READ / WRITE
Internal Address
(SA3 - SA1)
Internally Addressed Device EEPROM Array CONSTAT Register DCP
000 010 111
Bit SA0 0 1
Operation WRITE READ
Figure 4.
Slave Address Format
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Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either the EEPROM array, the Non Volatile Memory of a DCP (NVM), or the CONSTAT Register) has been correctly issued (including the final STOP condition), the X9521 initiates an internal high voltage write cycle. This cycle typically requires 5 ms. During this time, no further Read or Write commands can be issued to the device. Write Acknowledge Polling is used to determine when this high voltage write cycle has been completed. To perform acknowledge polling, the master issues a START condition followed by a Slave Address Byte. The Slave Address issued must contain a valid Internal Device Address. The LSB of the Slave Address (R/W) can be set to either 1 or 0 in this case. If the device is still busy with the high voltage cycle then no ACKNOWLEDGE will be returned. If the device has completed the write operation, an ACKNOWLEDGE will be returned and the host can then proceed with a read or write operation. (Refer to Figure 5.).
N RHx
WIPER COUNTER REGISTER (WCR) DECODER "WIPER" FET SWITCHES RESISTOR ARRAY
NON VOLATILE MEMORY (NVM)
2 1 0 RLx RWx
Figure 6.
DCP Internal Structure
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
Byte load completed by issuing STOP. Enter ACK Polling
Issue START
The X9521 includes two independent resistor arrays. These arrays respectively contain 99 and 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RHx and RLx inputs - where x = 1,2).
Issue STOP
Issue Slave Address Byte (Read or Write)
ACK returned? YES High Voltage Cycle complete. Continue command sequence? YES Continue normal Read or Write command sequence
NO
At both ends of each array and between each resistor segment there is a CMOS switch connected to the wiper (Rwx) output. Within each individual array, only one switch may be turned on at any one time. These switches are controlled by the Wiper Counter Register (WCR) (See Figure 6). The WCR is a volatile register. On power-up of the X9521, wiper position data is automatically loaded into the WCR from its associated Non Volatile Memory (NVM) Register. The Table below shows the Initial Values of the DCP WCR's before the contents of the NVM is loaded into the WCR.
DCP R1 / 100 TAP R2 / 256 TAP Initial Values Before Recall VL / TAP = 0 VH / TAP = 255
NO Issue STOP
PROCEED
Figure 5.
Acknowledge Polling Sequence
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Vcc
Vcc (Max.) VTRIP
ttrans
tpu
t
0
Maximum Wiper Recall time
Figure 7.
DCP Power-up remains unchanged. Therefore, when Vcc to the device is powered down then back up, the "wiper position" reverts to that last position written to the DCP using a nonvolatile write operation. Both volatile and nonvolatile write operations are executed using a three byte command sequence: (DCP) Slave Address Byte, Instruction Byte, followed by a Data Byte (See Figure 9). A DCP Read operation allows the user to "read out" the current "wiper position" of the DCP, as stored in the associated WCR. This operation is executed using the Random Address Read command sequence, consisting of the (DCP) Slave Address Byte followed by an Instruction Byte and the Slave Address Byte again (Refer to Figure 11.).
The data in the WCR is then decoded to select and enable one of the respective FET switches. A "make before break" sequence is used internally for the FET switches when the wiper is moved from one tap position to another.
Hot Pluggability
Figure 7 shows a typical waveform that the X9521 might experience in a Hot Pluggable situation. On power-up, Vcc applied to the X9521 may exhibit some amount of ringing, before it settles to the required value. The device is designed such that the wiper terminal (RWx) is recalled to the correct position (as per the last stored in the DCP NVM), when the voltage applied to Vcc exceeds VTRIP for a time exceeding tpu. Therefore, if ttrans is defined as the time taken for Vcc to settle above VTRIP (Figure 7): then the desired wiper terminal position is recalled by (a maximum) time: ttrans + tpu. It should be noted that ttrans is determined by system hot plug conditions.
Instruction Byte
While the Slave Address Byte is used to select the DCP devices, an Instruction Byte is used to determine which DCP is being addressed. The Instruction Byte (Figure 8) is valid only when the Device Type Identifier and the Internal Device Address bits of the Slave Address are set to 1010111. In this case, the two Least Significant Bit's (I1 - I0) of the Instruction Byte are used to select the particular DCP (0 - 2). In the case of a Write to any of the DCPs (i.e. the LSB of the Slave Address is 0), the Most Significant Bit of the Instruction Byte (I7), determines the Write Type (WT) performed. If WT is "1", then a Nonvolatile Write to the DCP occurs. In this case, the "wiper position" of the DCP is changed by simultaneously writing new data to the associated WCR and NVM. Therefore, the new "wiper position" setting is recalled into the WCR after Vcc of the X9521 has been powered down then powered back up
DCP Operations
In total there are three operations that can be performed on any internal DCP structure: --DCP Nonvolatile Write --DCP Volatile Write --DCP Read A nonvolatile write to a DCP will change the "wiper position" by simultaneously writing new data to the associated WCR and NVM. Therefore, the new "wiper position" setting is recalled into the WCR after Vcc of the X9521 is powered down and then powered back up. A volatile write operation to a DCP however, changes the "wiper position" by writing new data to the associated WCR only. The contents of the associated NVM register
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I7
WT
I6
0
I5
0
I4
0
I3
0
I2
0
I1
P1
I0
P0
volatile or nonvolatile. If the Instruction Byte format is valid, another ACKNOWLEDGE is then returned by the X9521. Following the Instruction Byte, a Data Byte is issued to the X9521 over SDA. The Data Byte contents is latched into the WCR of the DCP on the first rising edge of the clock signal, after the LSB of the Data Byte (D0) has been issued on SDA (See Figure 25). The Data Byte determines the "wiper position" (which FET switch of the DCP resistive array is switched ON) of the DCP. The maximum value for the Data Byte depends upon which DCP is being addressed (see Table below).
P1 - P0 0 0 1 1 0 1 0 1 x=1 x=2 DCPx # Taps Reserved 100 256 Reserved Refer to Appendix 1 FFh Max. Data Byte
WRITE TYPE
DCP SELECT
WT 0 1
Description Select a Volatile Write operation to be performed on the DCP pointed to by bits P1 and P0 Select a Nonvolatile Write operation to be performed on the DCP pointed to by bits P1 and P0
This bit has no effect when a Read operation is being performed.
Figure 8.
Instruction Byte Format
If WT is "0" then a DCP Volatile Write is performed. This operation changes the DCP "wiper position" by writing new data to the associated WCR only. The contents of the associated NVM register remains unchanged. Therefore, when Vcc to the device is powered down then back up, the "wiper position" reverts to that last written to the DCP using a nonvolatile write operation.
Using a Data Byte larger than the values specified above results in the "wiper terminal" being set to the highest tap position. The "wiper position" does NOT roll-over to the lowest tap position. For DCP2 (256 Tap), the Data Byte maps one to one to the "wiper position" of the DCP "wiper terminal". Therefore, the Data Byte 00001111 (1510) corresponds to setting the "wiper terminal" to tap position 15. Similarly, the Data Byte 00011100 (2810) corresponds to setting the "wiper terminal" to tap position 28. The mapping of the Data Byte to "wiper position" data for DCP1 (100 Tap), is shown in "APPENDIX 1" . An example of a simple C language function which "translates" between the tap position (decimal) and the Data Byte (binary) for DCP1, is given in "APPENDIX 2" . It should be noted that all writes to any DCP of the X9521 are random in nature. Therefore, the Data Byte of consecutive write operations to any DCP can differ by an arbitrary number of bits. Also, setting the bits (P1 = 0,
DCP Write Operation
A write to DCPx (x = 1,2) can be performed using the three byte command sequence shown in Figure 9. In order to perform a write operation on a particular DCP, the Write Enable Latch (WEL) bit of the CONSTAT Register must first be set (See "BL1, BL0: Block Lock protection bits - (Nonvolatile)" on page 12.) The Slave Address Byte 10101110 specifies that a Write to a DCP is to be conducted. An ACKNOWLEDGE is returned by the X9521 after the Slave Address, if it has been received correctly. Next, an Instruction Byte is issued on SDA. Bits P1 and P0 of the Instruction Byte determine which WCR is to be written, while the WT bit determines if the Write is to be
S1 T A R T
0
1
0
1
1
1
0
A WT C K
0
0
0
0
0
P1 P0
A C K
D7 D6 D5 D4 D3 D2 D1 D0
A C K
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
S T O P
Figure 9.
DCP Write Command Sequence
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S t a r t
Signals from the Master
(2 < n < 16) Slave Address Address Byte Data (1) Data (n)
S t o p
SDA Bus Signals from the Slave
1 01 00 00 0
A C K A C K A C K A C K
Figure 10. EEPROM Page Write Operation P0 = 0) or (P1 = 1, P0 = 1) are reserved sequences, and will result in no ACKNOWLEDGE after sending an Instruction Byte on SDA. The factory default setting of all "wiper position" settings is with 00h stored in the NVM of the DCPs. This corresponds to having the "wiper teminal" RWX (x=1,2) at the "lowest" tap position, Therefore, the resistance between RWX and RLX is a minimum (essentially only the Wiper Resistance, RW). an Instruction Byte is issued on SDA. Bits P1 - P0 of the Instruction Byte determine which DCP "wiper position" is to be read. In this case, the state of the WT bit is "don't care". If the Instruction Byte format is valid, then another ACKNOWLEDGE is returned by the X9521. Following this ACKNOWLEDGE, the master immediately issues another START condition and a valid Slave address byte with the R/W bit set to 1. Then the X9521 issues an ACKNOWLEDGE followed by Data Byte, and finally, the master issues a STOP condition. The Data Byte read in this operation, corresponds to the "wiper position" (value of the WCR) of the DCP pointed to by bits P1 and P0. It should be noted that when reading out the data byte for DCP1 (100 Tap), the upper most significant bit is an "unknown". For DCP2 (256 Tap) however, all bits of the data byte are relevant (See Figure 11).
DCP Read Operation
A read of DCPx (x = 1,2) can be performed using the three byte random read command sequence shown in Figure 11. The master issues the START condition and the Slave Address Byte 10101110 which specifies that a "dummy" write" is to be conducted. This "dummy" write operation sets which DCP is to be read (in the preceding Read operation). An ACKNOWLEDGE is returned by the X9521 after the Slave Address if received correctly. Next,
Signals from the Master SDA Bus Signals from the Slave
S t a r t
WRITE Operation
Slave Address
Instruction Byte
W 00000 P P 10 T
A C K A C K
S t a r t
READ Operation
Slave Address
Data Byte
S t o p
10101110
10101111
A C K
DCPx
-
x=1 x=2
LSB
"Dummy" write
MSB
"-" = DON'T CARE
Figure 11.
DCP Read Sequence
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S t a r t
Signals from the Master SDA Bus Signals from the Slave
WRITE Operation
Slave Address
Address Byte
Data Byte
S t o p
1 01 00 00 0
Internal Device Address
A C K
A C K
A C K
Figure 12. EEPROM Byte Write Sequence
2kbit EEPROM ARRAY Operations on the 2kbit EEPROM Array, consist of either 1, 2 or 3 byte command sequences. All operations on the EEPROM must begin with the Device Type Identifier of the Slave Address set to 1010000. A Read or Write to the EEPROM is selected by setting the LSB of the Slave Address to the appropriate value R/W (Read = "1", Write = "0"). In some cases when performing a Read or Write to the EEPROM, an Address Byte may also need to be specified. This Address Byte can contain the values 00h to FFh. EEPROM Byte Write In order to perform an EEPROM Byte Write operation to the EEPROM array, the Write Enable Latch (WEL) bit of the CONSTAT Register must first be set (See "BL1, BL0: Block Lock protection bits - (Nonvolatile)" on page 12.) For a write operation, the X9521 requires the Slave Address Byte and an Address Byte. This gives the master access to any one of the words in the array. After receipt of the Address Byte, the X9521 responds with an ACKNOWLEDGE, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, it again responds with an ACKNOWLEDGE. The master then terminates the transfer by generating a STOP condition, at which time the X9521 begins the internal write cycle to the nonvolatile memory (See Figure 12). During this internal write cycle, the X9521 inputs are disabled, so it does not respond to any requests from the master. The SDA output is at high impedance. A write to a region of EEPROM memory which has been protected with the Block-Lock feature (See "BL1, BL0: Block Lock protection bits - (Nonvolatile)" on page 12.), suppresses the ACKNOWLEDGE bit after the Address Byte.
EEPROM Page Write
In order to perform an EEPROM Page Write operation to the EEPROM array, the Write Enable Latch (WEL) bit of the CONSTAT Register must first be set (See "BL1, BL0: Block Lock protection bits - (Nonvolatile)" on page 12.) The X9521 is capable of a page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the X9521 responds with an ACKNOWLEDGE, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and goes back to `0' on the same page. For example, if the master writes 12 bytes to the page starting at location 11 (decimal), the first 5 bytes are written to locations 11 through 15, while the last 7 bytes are written to locations 0 through 6. Afterwards, the address counter would point to location 7. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time (See Figure 13). The master terminates the Data Byte loading by issuing a STOP condition, which causes the X9521 to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. See Figure 10 for the address, ACKNOWLEDGE, and data transfer sequence.
Stops and EEPROM Write Modes
Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and receiving the subsequent ACKNOWLEDGE signal. If the master issues a STOP within a Data Byte, or before the X9521 issues a corresponding ACKNOWLEDGE, the X9521 cancels the write operation. Therefore, the contents of the EEPROM array does not change.
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7 bytes
5 bytes 5 bytes
address = 6 10 address pointer ends here Addr = 710
address 1110
address 1510
Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.
Signals from the Master
S t a r t
Slave Address 1 01 0 0 0 0 1 A C K Data
S t o p
SDA Bus Signals from the Slave
Figure 14. Current EEPROM Address Read Sequence
EEPROM Array Read Operations
Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current EEPROM Address Read, Random EEPROM Read, and Sequential EEPROM Read.
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a STOP condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a STOP condition. Another important point to note regarding the "Current EEPROM Address Read" , is that this operation is not available if the last executed operation was an access to a DCP or the CONSTAT Register (i.e.: an operation using the Device Type Identifier 1010111 or 1010010). Immediately after an operation to a DCP or CONSTAT Register is performed, only a "Random EEPROM Read" is available. Immediately following a "Random EEPROM Read" , a "Current EEPROM Address Read" or "Sequential EEPROM Read" is once again available (assuming that no access to a DCP or CONSTAT Register occur in the interim).
Current EEPROM Address Read
Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an ACKNOWLEDGE and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an ACKNOWLEDGE during the ninth clock and then issues a STOP condition (See Figure 14 for the address, ACKNOWLEDGE, and data transfer sequence).
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Signals from the Master SDA Bus Signals from the Slave
S t a r t
WRITE Operation
Slave Address
Address Byte
S t Slave a r Address t 10100001
READ Operation
S t o p
10 1 0 0 0 0 0 A C K
"Dummy" Write
A C K
A C K
Data
Figure 15. Random EEPROM Address Read Sequence
Random EEPROM Read
Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the START condition and the Slave Address Byte, receives an ACKNOWLEDGE, then issues an Address Byte. This "dummy" Write operation sets the address pointer to the address from which to begin the random EEPROM read operation. After the X9521 acknowledges the receipt of the Address Byte, the master immediately issues another START condition and the Slave Address Byte with the R/W bit set to one. This is followed by an ACKNOWLEDGE from the X9521 and then by the eight bit word. The master terminates the read operation by not responding with an ACKNOWLEDGE and instead issuing a STOP condition (Refer to Figure 15.). A similar operation called "Set Current Address" also exists. This operation is performed if a STOP is issued instead of the second START shown in Figure 15. In this case, the device sets the address pointer to that of the
Address Byte, and then goes into standby mode after the STOP bit. All bus activity will be ignored until another START is detected.
Sequential EEPROM Read
Sequential reads can be initiated as either a current address read or random address read. The first Data Byte is transmitted as with the other modes; however, the master now responds with an ACKNOWLEDGE, indicating it requires additional data. The X9521 continues to output a Data Byte for each ACKNOWLEDGE received. The master terminates the read operation by not responding with an ACKNOWLEDGE and instead issuing a STOP condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through the entire memory contents to be serially read during one operation. At the end of the address space the counter "rolls over" to address 00h and the device continues to output data for each ACKNOWLEDGE received (Refer to Figure 16.).
Signals from the Master SDA Bus Signals from the Slave
Slave Address 0 0 01 A C K Data (1)
A C K
A C K
A C K
S t o p
Data (2)
Data (n) (n is any integer greater than 1)
Data (n - 1)
Figure 16. Sequential EEPROM Read Sequence
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X9521
The WEL bit is a volatile latch that powers up in the disabled, LOW (0) state. The WEL bit is enabled / set by writing 00000010 to the CONSTAT register. Once enabled, the WEL bit remains set to "1" until either it is reset to "0" (by writing 00000000 to the CONSTAT register) or until the X9521 powers down, and then up again. Writes to the WEL bit do not cause an internal high voltage write cycle. Therefore, the device is ready for another operation immediately after a STOP condition is executed in the CONSTAT Write command sequence (See Figure 18). RWEL: Register Write Enable Latch (Volatile) The RWEL bit controls the (CONSTAT) Register Write Enable status of the X9521. Therefore, in order to write to any of the bits of the CONSTAT Register (except WEL), the RWEL bit must first be set to "1". The RWEL bit is a volatile bit that powers up in the disabled, LOW ("0") state. It must be noted that the RWEL bit can only be set, once the WEL bit has first been enabled (See "CONSTAT Register Write Operation"). The RWEL bit will reset itself to the default "0" state, in one of three cases: --After a successful write operation to any bits of the CONSTAT register has been completed (See Figure 18). --When the X9521 is powered down. --When attempting to write to a Block Lock protected region of the EEPROM memory (See "BL1, BL0: Block Lock protection bits - (Nonvolatile)", below). BL1, BL0: Block Lock protection bits - (Nonvolatile) The Block Lock protection bits (BL1 and BL0) are used to: --Inhibit a write operation from being performed to certain addresses of the EEPROM memory array --Inhibit a DCP write operation (changing the "wiper position").
CS7
0
CS6
0
CS5
0
CS4
BL1 NV
CS3
BL0 NV
CS2
RWEL
CS1
WEL
CS0
0
Bit(s) CS7 - CS5 BL1 - BL0 RWEL WEL CS0
Description Always "0"(RESERVED) Sets the Block Lock partition Register Write Enable Latch bit Write Enable Latch bit Always "0" (RESERVED)
NOTE: Bits labelled NV are nonvolatile (See "CONTROL AND STATUS REGISTER").
Figure 17. CONSTAT Register Format
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register provides the user with a mechanism for changing and reading the status of various parameters of the X9521 (See Figure 17). The CONSTAT register is a combination of both volatile and nonvolatile bits. The nonvolatile bits of the CONSTAT register retain their stored values even when Vcc is powered down, then powered back up. The volatile bits however, will always power-up to a known logic state "0" (irrespective of their value at power-down). A detailed description of the function of each of the CONSTAT register bits follows: WEL: Write Enable Latch (Volatile) The WEL bit controls the Write Enable status of the entire X9521 device. This bit must first be enabled before ANY write operation (to DCPs, EEPROM memory array, or the CONSTAT register). If the WEL bit is not first enabled, then ANY proceeding (volatile or nonvolatile) write operation to DCPs, EEPROM array, as well as the CONSTAT register, is aborted and no ACKNOWLEDGE is issued after a Data Byte.
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FN8207.1 January 3, 2006
X9521
SCL
SDA S T A R T 1 0 1 0 0 1 0 R/W A C K 1 1 1 1 1 1 1 1 A C K CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 A C K S T O P
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA IN
Figure 18. CONSTAT Register Write Command Sequence
The region of EEPROM memory which is protected / locked is determined by the combination of the BL1 and BL0 bits written to the CONSTAT register. It is possible to lock the regions of EEPROM memory shown in the table below:
BL1 BL0 0 0 1 1 0 1 0 1 Protected Addresses (Size) None (Default) C0h - FFh (64 bytes) 80h - FFh (128 bytes) 00h - FFh (256 bytes) Partition of array locked None (Default) Upper 1/4 Upper 1/2 All
Only one data byte is allowed to be written for each CONSTAT register Write operation. The user must issue a STOP, after sending this byte to the register, to initiate the nonvolatile cycle that stores the BP1and BP0 bits. The X9521 will not ACKNOWLEDGE any data bytes written after the first byte is entered (Refer to Figure 18.). When writing to the CONSTAT register, the bits CS7CS5 and CS0 must all be set to "0". Writing any other bit sequence to bits CS7-CS5 and CS0 of the CONSTAT register is reserved. Prior to writing to the CONSTAT register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps --Write a 02H to the CONSTAT Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a START and ended with a STOP). --Write a 06H to the CONSTAT Register to set the Register Write Enable Latch (RWEL) AND the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceded by a START and ended with a STOP). --Write a one byte value to the CONSTAT Register that has all the bits set to the desired state. The CONSTAT register can be represented as 000st010 in binary, where st are the Block Lock Protection (BL1 and BL0) bits. This operation is proceeded by a START and ended with a STOP bit. Since this is a nonvolatile write cycle, it will typically take 5ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to `1' in this third step (000s t110) then the RWEL bit is set, but the BL1 and BL0 bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and the X9521 does not return an ACKNOWLEDGE.
If the user attempts to perform a write operation on a protected region of EEPROM memory, the operation is aborted without changing any data in the array. When the Block Lock bits of the CONSTAT register are set to something other than BL1 = 0 and BL0 = 0, then the "wiper position" of the DCPs cannot be changed - i.e. DCP write operations cannot be conducted:
BL1 0 0 1 1 BL0 0 1 0 1 DCP Write Operation Permissible YES (Default) NO NO NO
The factory default setting for these bits are BL1 = 0, BL0 = 0. IMPORTANT NOTE: If the Write Protect (WP) pin of the X9521 is active (HIGH), then all nonvolatile write operations to both the EEPROM memory and DCPs are inhibited, irrespective of the Block Lock bit settings (See "WP: Write Protection Pin").
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave Address set to 1010010 (Refer to Figure 4.). Following the Slave Address Byte, access to the CONSTAT register requires an Address Byte which must be set to FFh.
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FN8207.1 January 3, 2006
X9521
WRITE Operation READ Operation
Signals from the Master SDA Bus Signals from the Slave
S t a r t
Slave Address
Address Byte
S t Slave a r Address t
CS7 ... CS0 A C K
S t o p
10 1 0 0 1 0 0 A C K
"Dummy" Write
10 1 0 0 1 01 A C K Data
Figure 19. CONSTAT Register Read Command Sequence For example, a sequence of writes to the device CONSTAT register consisting of [02H, 06H, 02H] will reset the BL0 and BL0 bits in the CONSTAT Register to "0". It should be noted that a write to any nonvolatile bit of CONSTAT register will be ignored if the Write Protect pin of the X9521 is active (HIGH) (See "WP: Write Protection Pin"). DATA PROTECTION There are a number of levels of data protection features designed into the X9521. Any write to the device first requires setting of the WEL bit in the CONSTAT register. A write to the CONSTAT register itself, further requires the setting of the RWEL bit. Block Lock protection of the device enables the user to inhibit writes to certain regions of the EEPROM memory, as well as to all the DCPs. One further level of data protection in the X9521, is incorporated in the form of the Write Protection pin.
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at any time by performing a random read (See Figure 19). Using the Slave Address Byte set to 10100101, and an Address Byte of FFh. Only one byte is read by each register read operation. The X9521 resets itself after the first byte is read. The master should supply a STOP condition to be consistent with the bus protocol. After setting the WEL and / or the RWEL bit(s) to a "1", a CONSTAT register read operation may occur, without interrupting a proceeding CONSTAT register write operation. When reading the contents of the CONSTAT register, the bits CS7 - CS5 and CS0 will always return "0".
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it disables nonvolatile write operations to the X9521. The table below (X9521 Write Permission Status) summarizes the effect of the WP pin (and Block Lock), on the write permission status of the device.
Additional Data Protection Features
In addition to the preceding features, the X9521 also incorporates the following data protection functionality: --The proper clock count and data bit sequence is required prior to the STOP bit in order to start a nonvolatile write cycle.
X9521 Write Permission Status
Block Lock Bits BL0 x 1 0 x 1 0 BL1 1 x 0 1 x 0 WP 1 1 1 0 DCP Volatile Write Permitted NO NO YES NO NO YES DCP Nonvolatile Write Permitted NO NO NO NO NO YES Write to EEPROM Permitted NO NO NO Not in locked region Not in locked region Yes (All Array) Write to CONSTAT Register Permitted Volatile Bits NO NO NO YES YES YES Nonvolatile Bits NO NO NO YES YES YES
0 0
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FN8207.1 January 3, 2006
X9521
ABSOLUTE MAXIMUM RATINGS
Parameter Min. Max. Units
Temperature under Bias Storage Temperature Voltage on WP pin (With respect to Vss) Voltage on other pins (With respect to Vss) | Voltage on RHx - Voltage on RLx | (x = 1,2. Referenced to Vss) D.C. Output Current (SDA) Lead Temperature (Soldering, 10 seconds) Supply Voltage Limits (Applied Vcc voltage, referenced to Vss) RECOMMENDED OPERATING CONDITIONS
Temperature Industrial
-65 -65 -1.0 -1.0
0
2.7
+135 +150 +15 +7 Vcc 5 300 5.5
C C V V V mA C V
Min. -40
Max. +85
Units
C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Figure 20. Equivalent A.C. Circuit
Vcc = 5V 2300 SDA 100pF
Figure 21. DCP SPICE Macromodel
RTOTAL CH 10pF CL RW CW 25pF RWx
(x = 1,2)
RHx
RLx
10pF
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FN8207.1 January 3, 2006
X9521
TIMING DIAGRAMS Figure 22. Bus Timing tF SCL tSU:ST SDA IN SDA OUT tHD:STA tSU:DAT tHD:DAT tA tDH tBUF tSU:STO tHIGH tLOW tR
Figure 23. WP Pin Timing START SCL SDA IN WP tSU:WP tHD:WP Clk 1 Clk 9
Figure 24. Write Cycle Timing SCL SDA 8th bit of last byte ACK tWC Stop Condition Start Condition
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FN8207.1 January 3, 2006
X9521
Figure 25. DCP "Wiper Position" Timing
Rwx (x = 1,2)
Rwx(n)
Rwx(n + 1) Rwx(n - 1)
twr
n = tap position
SCL
Time
SDA
S1 T A R T 0 1 0 1 1 1 0 A WT C K 0 0 0 0 0 P1 P0 A C K D7 D6 D5 D4 D3 D2 D1 D0 A C K S T O P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
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X9521
D.C. OPERATING CHARACTERISTICS
Symbol ICC1(1) Parameter Current into VCC Pin (X9521: Active) Read memory array (3) Write nonvolatile memory Min Typ Max Unit Test Conditions / Notes fSCL = 400kHz VSDA = VCC WP = Vss or Open/Floating VSCL= VCC (when no bus activity else fSCL = 400kHz) VIN (4) = GND to VCC. VIN = VSS to VCC with all other analog pins floating X9521 is in Standby(2) VOUT (5) = GND to VCC.
0.4 1.5
mA
Current into VCC Pin ICC2(2)
(X9521:Standby) With 2-Wire bus activity (3) No 2-Wire bus activity 0.1
50 50 10 10 1 0.1 -0.5 2.0 10 10 0.8 VCC +0.5 0.4
A
ILI Iai ILO VIL (6) VIH (6) VOLx
Input Leakage Current (SCL, SDA) Input Leakage Current (WP) Analog Input Leakage Output Leakage Current (SDA) Input LOW Voltage (SCL, SDA, WP) Input HIGH Voltage (SCL,SDA, WP) SDA Output Low Voltage
A A A A V V V
ISINK = 2.0mA
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200nS after a STOP ending a read operation; or tWC after a STOP ending a write operation. Notes: 2.The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; tWC after a STOP that initiates a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte. Notes: 3.Current through external pull up resistor not included. Notes: 4.VIN = Voltage applied to input pin. Notes: 5.VOUT = Voltage applied to output pin. Notes: 6.VIL Min. and VIH Max. are for reference only and are not tested.
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FN8207.1 January 3, 2006
X9521
A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)
400kHz Symbol fSCL tIN (5) tAA (5) tBUF (5) tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH
(5)
Parameter SCL Clock Frequency Pulse width Suppression Time at inputs SCL LOW to SDA Data Out Valid Time the bus free before start of new transmission Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time SDA and SCL Rise Time SDA and SCL Fall Time WP Setup Time WP Hold Time Capacitive load for each bus line
Min 0 50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 20 +.1Cb (2) 20 +.1Cb (2) 0.6 0
Max 400
Units kHz ns
0.9
s s s s s s ns s s ns
tR (5) tF (5) tSU:WP tHD:WP Cb
300 300
ns ns s s
400
pF
A.C. TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load 0.1VCC to 0.9VCC 10ns 0.5VCC See Figure 20
NONVOLATILE WRITE CYCLE TIMING
Symbol tWC(4) Parameter Nonvolatile Write Cycle Time Min. Typ.(1) 5 Max. 10 Units ms
CAPACITANCE (TA = 25C, f = 1.0 MHz, VCC = 5V)
Symbol COUT (5) CIN (5) Parameter Output Capacitance (SDA, V1RO, V2RO, V3RO) Input Capacitance (SCL, WP) Max 8 6 Units pF pF Test Conditions VOUT = 0V VIN = 0V
Notes: 1. Typical values are for TA = 25C and VCC = 5.0V Notes: 2.Cb = total capacitance of one bus line in pF. Notes: 3.Over recommended operating conditions, unless otherwise specified Notes: 4.tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Notes: 5.This parameter is not 100% tested.
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FN8207.1 January 3, 2006
X9521
POTENTIOMETER CHARACTERISTICS
Limits Symbol RTOL VRHx VRLx PR Parameter End to End Resistance Tolerance RH Terminal Voltage (x = 1,2) RL Terminal Voltage (x = 1,2) Power Rating (1)(6) Min. -20 Vss Vss Typ. Max. +20 VCC VCC 10 5 200 RW DCP Wiper Resistance 400 IW Wiper Current (6) Noise Absolute Linearity (2) Relative Linearity (3) RTOTAL Temperature Coefficient CH/CL/CW twcr VTRIP tPU Potentiometer Capacitances Wiper Response time (6) Vcc power-up DCP recall threshold Vcc power-up DCP recall delay time (6) 25 50 75 1200 4.4 mA mV/ sqt(Hz) mV/ sqt(Hz) -1 -1 300 300 10/10/25 200 +1 +1 MI(4) MI(4) ppm/C ppm/C pF s V ms RTOTAL = 10k ( DCP1) RTOTAL = 100k (DCP2) Rw(n)(actual) - Rw(n)(expected) Rw(n + 1) - [Rw(n) + MI] RTOTAL = 10k (DCP1) RTOTAL = 100k (DCP2) See Figure 21. See Figure 25. 400 Units % V V mW mW RTOTAL = 10k (DCP1) RTOTAL = 100k (DCP2) IW = 1mA, VCC = 5 V, VRHx = Vcc, VRLx = Vss (x = 1,2). IW = 1mA, VCC = 2.7 V, VRHx = Vcc, VRLx = Vss (x = 1,2) Test Conditions/Notes
Notes: 1. Power Rating between the wiper terminal RWX(n) and the end terminals RHX or RLX - for ANY tap position n, (x = 1,2). Notes: 2.Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (Rwx(n)(actual) - Rwx(n)(expected)) = 1 Ml Maximum (x = 1,2). Notes: 3.Relative Linearity is a measure of the error in step size between taps = RWx(n + 1) - [Rwx(n) + Ml] = 1 Ml (x = 0,1,2) Notes: 4.1 Ml = Minimum Increment = RTOT / (Number of taps in DCP - 1). Notes: 5.Typical values are for TA = 25C and nominal supply voltage. Notes: 6.This parameter is periodically sampled and not 100% tested.
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FN8207.1 January 3, 2006
X9521
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Tap Position 0 1 . . 23 24 25 26 . . 48 49 50 51 . . 73 74 75 76 . . 98 99 Data Byte Decimal 0 1 . . 23 24 56 55 . . 33 32 64 65 . . 87 88 120 119 . . 97 96 Binary 0000 0000 0000 0001 . . 0001 0111 0001 1000 0011 1000 0011 0111 . . 0010 0001 0010 0000 0100 0000 0100 0001 . . 0101 0111 0101 1000 0111 1000 0111 0111 . . 0110 0001 0110 0000
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FN8207.1 January 3, 2006
X9521
APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)
unsigned { int int int int
DCP1_TAP_Position(int tap_pos) block; i; offset; wcr_val;
offset= 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); else if (block <= 3) { switch(block) { case (0): return ((unsigned)tap_pos) ; case (1): { wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); } case (2): { wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned)--wcr_val); } case (3): { wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); } } } return((unsigned)01100000); }
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FN8207.1 January 3, 2006
X9521
APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)
unsigned DCP100_TAP_Position(int tap_pos) { /* optional range checking */ if (tap_pos < 0) return ((unsigned)0); else if (tap_pos >99) return ((unsigned) 96); /* 100 Tap DCP encoding formula */ if (tap_pos > 74) return ((unsigned) (195 - tap_pos)); else if (tap_pos > 49) return ((unsigned) (14 + tap_pos)); else if (tap_pos > 24) return ((unsigned) (81 - tap_pos)); else return (tap_pos); }
/* set to min val */ /* set to max val */
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FN8207.1 January 3, 2006
X9521
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.252 (6.4) .260 (6.6)
.047 (1.20) .0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane (1.78) (0.42) (0.65)
(4.16)
(7.72)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 24
FN8207.1 January 3, 2006

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